Current Issue : July-September Volume : 2022 Issue Number : 3 Articles : 5 Articles
In this paper, a low-profile, compact size, inexpensive, and easily integrable frequency reconfigurable antenna system is proposed. The proposed antenna consists of an inverted-F shape antenna, capacitors, and switching PIN diodes. The designed antenna element is fabricated on easy available and less expensive FR-4 substrate (εr 4.4, tan δ 0.02). The switching diodes are incorporated within the radiating structure of the antenna design, and by changing the different states of PIN diodes, frequency reconfigurable response is achieved. While adjusting the different states of the diodes, the antenna resonates between 0.841 GHz and 2.12 GHz and covers six different frequency bands. The proposed system has compact size of 44 × 14 × 3.2mm3. The gain of the antenna is between 1.89 and 2.12 dBi. The measurement results shows the good agreement with simulated results for different key performance parameters. Additionally, the proposed antenna shows omni-directional far-field characteristics for various different frequencies....
A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated....
A circularly polarized (CP) broadside antenna array with a continuously adjustable beam is proposed and implemented. First, a reflection phase shifter with varactor diodes loaded on two output terminals of a branch directional coupler is realized. By controlling the voltage across both ends of the varactor diodes in the terminal load circuit, the reactance of the load is changed, allowing control of port phase shift. Following that, the microstrip patch antenna array is combined with the reflection phase shifter to achieve the pattern reconstruction for the array. For verification, a prototype of the designed pattern reconfigurable antenna (PRA) is fabricated and measured. The measurement results indicate that the beam direction of the antenna can be continuously adjusted with a change in the voltage across the varactor diodes. The maximum beam direction of the antenna reaches ±21° when the biggest DC bias voltage across the varactor diode is chosen as 15 V. Besides, the antenna shows good CP performance in different beam directions....
FPGA-based accelerators have shown great potential in improving the performance of CNN inference. However, the existing FPGA-based approaches suffer from a low compute unit (CU) efficiency due to their large number of redundant computations, thus leading to high levels of performance degradation. In this paper, we show that no single CU can perform best across all the convolutional layers (CONV-layers). To this end, we propose the use of dual sizes of compute unit (DSCU), an approach that aims to accelerate CNN inference in FPGAs. The key idea of DSCU is to select the best combination of CUs via dynamic programming scheduling for each CONV-layer and then assemble each CONV-layer combination into a computing solution for the given CNN to deploy in FPGAs. The experimental results show that DSCU can achieve a performance density of 3.36 × 10−3 GOPs/slice on a Xilinx Zynq ZU3EG, which is 4.29 times higher than that achieved by other approaches....
The use of the Hough transforms to identify shapes or images has been extensively studied in the past using software for artificial intelligence applications. In this article, we present a generalization of the goal of shape recognition using the Hough transform, applied to a broader range of real problems. A software simulator was developed to generate input patterns (straight-lines) and test the ability of a generic low-latency system to identify these lines: first in a clean environment with no other inputs and then looking for the same lines as ambient background noise increases. In particular, the paper presents a study to optimize the implementation of the Hough transform algorithm in programmable digital devices, such as FPGAs. We investigated the ability of the Hough transform to discriminate straight-lines within a vast bundle of random lines, emulating a noisy environment. In more detail, the study follows an extensive investigation we recently conducted to recognize tracks of ionizing particles in high-energy physics. In this field, the lines can represent the trajectories of particles that must be immediately recognized as they are created in a particle detector. The main advantage of using FPGAs over any other component is their speed and low latency to investigate pattern recognition problems in a noisy environment. In fact, FPGAs guarantee a latency that increases linearly with the incoming data, while other solutions increase latency times more quickly. Furthermore, HT inherently adapts to incomplete input data sets, especially if resolutions are limited. Hence, an FPGA system that implements HT is inefficient for small sets of input data but becomes more cost-effective as the size of the input data increases. The document first presents an example that uses a large Accumulator consisting of 1100 × 600 Bins and several sets of input data to validate the Hough transform algorithm as random noise increases to 80% of input data. Then, a more specifically dedicated input set was chosen to emulate a real situation where a Xilinx UltraScale+ was to be used as the final target device. Thus, we have reduced the Accumulator to 280 × 280 Bins using a clock signal at 250 MHz and a few tens input points. Under these conditions, the behavior of the firmware matched the software simulations, confirming the feasibility of the HT implementation on FPGA....
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